Getting Started with VHDL on Linux (GHDL & GTKWave)

Getting Started with VHDL on Linux (GHDL & GTKWave)


Hey everyone and welcome to my VHDL guide In this video I will be going through the necessary steps for getting VHDL up and running on your system we will conclude this guide by designing a
simple logic circuit and simulating it all the links code and commands that I
used in this guide are listed in the description below however i highly recommend that you
follow along and type everything yourself it will really help you out in the long
gone i do want to point out this guide is specifically for Linux if you’re on a
Windows machine click here to check out my Windows
version of this guide instead so let’s get started the two programs you will need for this
guide is GHDL which is our VHDL compiler and simulator and GTKWave which
is our WaveForm Viewer. GTKWave is part of the gEDA software suite which
incorporates a number of other EDA tools however we won’t be touching any of the
other ones in this guide you can check out my other videos that talk about them
if you’re interested so let’s go ahead and install GHDL and
GTKWave i’m currently running Fedora 24 if
you’re using Fedora 22 and up you’ll be using the command the same commands Ii
do which is “su -c ‘dnf -y install ghdl gtkwave'” If you’re using Fedora 22 and up, this is the command you will be using. And let me type my password quick be installing now if you using fedora 21
and below you’ll be tightened the same command but it will be as you don’t see
any you’ll be using yum install ghd l th TL gtk wave instead of dnf so that’s the command you’ll be using if
you’re using the door 21 in below if you’re using a different linux distro
that uses a different package manager such as Boone – you’ll be using a
similar command but it would be pseudo and then it will be pseudo and then you
want apt-get install and then you’ll be specifying the ghd lng TK wave so
whichever list are you using that’s the command that you’ll be using so let’s go
ahead and install it now that we have everything installed we want to like
some code but before we actually like any vhdl code I want to create a working directory for
my code and any generated files that will be created as we go along so I’m going to go to my home directory
and then i’m going to creating their directory that i’m going to call ha4 half editor you can create that
they’re actually wherever you usually write your code and then i’m going to CD
to my half a directory using your favorite source code editor let’s create
the half adder vhdl code i’m going to use veen so let me just
create another command prompt window so you can see clearly over there i’m going to create the file using
themes so i’m going to go team eh eh . vhdl so that’s a half after that
vhdl you can use nano or any other source code editor that you like and so
let me go ahead and started the first thing we want to write of course is that
we are using the I Triple E library and from the I Triple E library we are going
to use the I Triple E standard logic signals 1164 at all and that tells it
that we want to use the package that deals with all that gives us all the
standard signals that will be using and we want to create the and let’s go ahead and start an entity
block entity and we’re going to call it ha4 half editor is we’re going to close
the entity block by aunt HHA and inside the entity block we’re
going to write a port claws and what the port Clause does and what the port
Clause does is it gives us the signature for our block is seen from the outside
world which in our case is going to have one input in mr go in and we’re gonna
and it’s going to be a single beat sedu logic and we’re going to have
another input to be and it’s also a single beat sdu logic and then we have 0
which is going to be our output and it also a single BTW logic and finally we
have a/c carry out which is also a CDU logic so what we have here is we have two
inputs a and B for half adder and then we have two outputs which is are some
and i’ll carry out so let’s go ahead and describe the
architecture for and then i’m going to call it behave off AJ for half adder is and then we
always start a block with beginning and then we can’t behave and inside the
architecture block we actually describe how r entity what is there how do the signals flow so
in our case since this is just a simple half other our output is 1 when either
is one or peas one but not when both so for example 0 plus 1 is going to be a
1 140 is going to be a 1 and 0 plus 0 is going to be a zero so we wanted to when
a is 1 or B but not both so that would be a ex or B and our carry out see ok there’s only one it’s both a and
B so not what either one but when both of them so it’s going to be a and B and
i’m going to go ahead and save the file and before we move on I want to check
out that i did not make any kind of a syntax error in my code so to do that I’m going to go ahead and
I’m going to invoke RG HDL compiler so I’m going to take g HDL and i’m going
to use the dash S which which does a syntax check only without compiling
anything so i’m going to do – yes and I’m going to give it a half later that
vhdl file and I’m going to hit enter now if we don’t get any messages then we know we’re good to go
unfortunately you’ll see that i have made a syntax error and he told me their
own line 11 on one we’re missing a semicolon
at the end of the port class and indeed here at the end of report Claus we are missing a semicolon so i’m going
to go ahead and add a semicolon I’m gonna save the file again and then
i’m going to run the HDL compiler – s command again and notice that this
time we have no syntax errors so we know that this fire at least synthetically is
correct we have not proven that the logic is
correct but at least syntax wise it’s correct not that we have a half error code
complete and we know that it is synthetically correct we want to prove that is also logically
correct because we have not proven that yet to do that we’re going to create
something called a test bench so let’s close this file and I’m going to create
another file and I’m going to call it ha4 half adder underscore TB . vhdl and
TV stands for test bench and then i’m going to start out with the same way library then we’re going to tell we want
the I Triple E library and we want to use the I Triple E . standard logic 1164
that all and we’re going to create an entity which were going to call h on
this Court TV now this is the traditional naming convention that is
used for naming test benches which is the name of the unit under test this is
called uu t or the unit under test followed by an underscore followed by TB
later own or if you’ve already discovered there are a number of large
sophisticated integrated development environments over there offered by the
various fpga companies such as a pair are and ceilings and in their in their
programs you can actually semi generate the test benches automatically and they
followed the same the very same naming convention as i do here which is the
unit under test for by honest cop followed by TB so let’s go ahead and continue with our
entity block and you’re right these and we’re going to close the entity blocked
by writing and half adder TB and you’ll notice that the entity block is empty that is it has no inputs going into it
and no outputs going out to out of it and the reason for this should be quite
clear to you because this is a complete unit on its own that is going to generate signals to a
half adder and it’s going to read the output signals form our half adder back
and it’s going to check that it is logically sound and because of that we
do not expect any signals coming into our test patch or going out of it so
it’s going to be empty however we need to actually write the
code to conduct a test so let’s go ahead and describe the architecture of our
test bench so we want architecture our texture I can’t spell and we’re going to call it
test off half editor that he underscored TB is when we close the architecture
blocked by running and test and inside the architecture block we’re going to
tell vhdl day we are going to use a half enter component so component AJ and we NT component lock component
component who meant and inside the component we have our port which what I
usually do is are usually copy the port directly from our entity block so i
normally copied verbatim the reason I do that is because they have to match and
if I don’t win if I copied verbatim then I know it matches a hundred percent and
I did not make any errors many people make a lot of errors in this specific
part so if you get it an error you such as something is not
bound correctly this is probably why because your
component doesn’t match the entity block so i copied verbatim mean I in here and
so I know that this is this matches exactly and now i’m going to describe
the number of signals so i’m going to create a signal for each input and each
output so I’m just going to name them the same thing as in our half adder so
i’m going to name them a beat oh and see and they are all STD logic so
they are all seeking single beat signals and let’s start the architecture itself
so i’m gonna type again and we’re going to create a port map and we’re going to
call it half adder when using the OHA entity AJ component and then we open up or trap and we’re simply connecting z our signal
a to the a input of our component of a half editor and we’re connecting RP
signal we’ve ever be input of a half and there
were connecting out no signal to the output of our half
editor oh and likewise we’re going to connect
the sea signal to the carry out of our former half air as well there you go and now we want to write the actual test
to see that logic is correct so to do that we want to create a process and the
reason we’re creating a process is because we want to on everything
sequentially so going to say process begin and then we close the process block by
typing and process and inside a process block we’re going to start with our first test
so in our first test I’m going to actually give both inputs a
strong unknown so I want to start out with both
a and B having an unknown signal sent today and i’m going to wait for we’re
going to wait for one nanosecond for you one nanosecond and after we wait that
one in a second we’re going to keep a zero and we’re
going to give being zero as well so the first test boy the first test I’m writing will check
what happens when I add 0 plus 0 and of course the end results will be a carry
out of 0 and a sum of zero and then we want to wait for one in a second and
then we’ll write another test we cheese this time 0 for a and 14 be i’m going to wait for one in a second
again and then we’re going to have one away and 0 4 B and then we’re going to
wait for one in a second as well and finally let’s just make this a
little bigger so you can see the entire code and finally we’re going to have a
is one in these also one and we’re going to wait for one in a
second after we wait that i’m going to write a simple assert
statement which is going to evaluate and i’m going to print the message that says
reached the end of test and then we have to put a final weight and notice that i
did not specify time and that will take a look that will tell the simulation
that i’m waiting for ever effectively ending a test bench so I’m going to save this file and i
want to point out yet practical test benches should be will not look exactly
like this they will probably have lots of if statements and lots of conditional
checks and they will go through exhaustively checking all the signals
and they will also be checking the output signals know that in our test
bench I did not do anything with our onc
signals and the reason for this is because the half adder is so simple we can just test it using the wave form
view where that we’ve installed earlier in real practical test benches you will have much more code here much
more a lot more assert statements and there will be checking everything
exhaustively so now that we finish our test bench I’m going to first run the GTL – s
underscore TB and i’m going to just see text test mice my test bench so notice that there are no error
messages so I know that Italy syntactically my test match is good to
go and what I’m going to do now is I’m
actually going to analyze our a half later and to do that we’re going
to use the – a switch we want to specify the half later that
the HTML file and let it executes once again if there are no problems you’ll see no messages so in my case I’m
good to go and I’m going to also analyze the test
bench file so we’re going to use the – a switch
again for our test bench and once again no messages so we’re good to go and I’m going to tell if we want to
analyze the she stands for elaborate so we want to actually build the simulation
for test bench so the way we do that is we do HDL – II to elaborate and then in here
we tell it which object we want to actually build and in our case it’s the
half enter AJ on this Court TV notice that we
don’t specify file so there is no file extension but we giving it as a unit we
want to elaborate which is a half adder which is
effectively this entity we’re trying to test so when I enter and it compiled and once
again if there are no error messages you good to go and now we want to
actually run a test bench so to do that I’m going to do GTL dish
are and then once again i give it the name of our object which is a half
better test bench and you’ll see that it rain and it did print something however
it is not an error message it’s actually our assertion error that
we have created which was reached and of tests that is it went through all these
tests and it made it here which evaluated false and which is why it
printed this out so this is good news they told us it our test match went went through and
executed however we actually want to check out
our waveform diagram so to do that will create something called a vcd file and
to do that we specify – – vc d equals and then we tell it the name
of the file we want to dump our time values into which is half adder . vcd
and when they enter and notice that the simulation went once again and he
executed my code and it printed the assert statement once again but this
kind this time if I check the listing of my directory you’ll notice that i have
generated a half other data vcd file we found vcd file generated let’s go ahead and inspect it so vc d
stands for value change dump enemies a dump of all these signals and their
values that have changed during a simulation so to view it will type gtk
wave and then we’ll give it our half adder tha that vcd file and this will
open up our GT Kate wave program which is a waveform few where and let’s make
this a little bigger and you’ll see on the upper left corner you have a half
and half adder and we want to drag to our signals interface the signals that
we want to check out which in our case is actually all of them so we want a and
bre puts the sum and the carryout and you are you’ll see that our units
actually starts with phantom seconds which are attempt to the negative 15 of
a second so this is a very very very small so 1 cor trillionth of a second
this is a very small unit and we have defined our test in terms of nanoseconds this is way too small for us so the way
you zoom out is you hold down the control on your keyboard and then you
can use the scroll wheel to scroll up and down and zoom in and out so i’m
going to scroll out and now we are in picoseconds which is still too small so
I’m going to continue to zoom out and there we go so i zoomed out to nanoseconds and now
you can see our signal changing so you notice that between 0 and 1 nanosecond we told the cast to give a and be a
strong unknown signal and therefore the output is irrelevant for us because it
is unknown the input and output is the inputs are
known so let’s go ahead and check our first actual test and that is between
one nanosecond – 90 seconds we gave that we gave our half enter two inputs which
are both 0 so we’re telling it + 0 + 0 and we get an output of 0 and a
carry out of 0 so the logic 40 40 is correct now between two nanoseconds and three
nano seconds we told it to add 0 + 1 + 0 + 1 is 1 and
it has no carry out so carry out of 0 so this is correct again between three nano
seconds and for nano seconds we gave it an input for a of 1 and b of
0 and once again one plus zero is one with that carry out of 0 and finally
between four and five nanoseconds we gave it an input of 14 a and 14 b and
the sum of one plus one is zero and we do have it carry out this
time so the logic for half later so I closes and I go back to a half
better at it anyway so the logic for half editor is sound this is it for this guide I hope you
we’re successful in following alone and getting everything to work correctly if
you got stuck on anything or you have any comments or questions to leave a
comment below I will try my best to answer them if you’re interested in
additional guides please check out my other videos in my
channel and don’t forget to Like and subscribe so thank you